library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.all;

entity mux_2 is
port(
		input1: in std_logic_vector(15 downto 0);
		input2: in std_logic_vector(15 downto 0);
		output: out std_logic_vector(15 downto 0);
		sel: in std_logic
	);
end entity mux_2;

architecture arch of mux_2 is

	signal v: std_logic_vector(15 downto 0);
	
begin 
	v <= input1 when sel = '0' else input2;
	output <= v;
end architecture arch;