library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

entity stack is
port(
		Data_in: in std_logic_vector(15 downto 0);
		Data_out: out std_logic_vector(15 downto 0);
		address: in std_logic_vector(7 downto 0);
		clk, wr: in std_logic
	);
end entity stack;

architecture arch of stack is

	type memory_element is array (0 to 255) of std_logic_vector(15 downto 0);

	signal memory: memory_element := (others => (others => '0'));
	signal temp: std_logic_vector(15 downto 0);

begin
	process(clk) is
	begin
		
		if(rising_edge(clk)) then
		
			if(wr = '1') then memory(to_integer(unsigned(address))) <= Data_in; end if;
						
			temp <= memory(to_integer(unsigned(address)));
			
		end if;
			
	end process;
	
	Data_out <= temp;
	
end architecture arch;