library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.all;
use ieee.std_logic_unsigned.all ;


entity sign_ext is
port(
		s1: in std_logic_vector(3 downto 0);
		s2: in std_logic_vector(3 downto 0);
		output: out std_logic_vector(15 downto 0)
	);
end entity sign_ext;

architecture arch of sign_ext is
	signal va: std_logic_vector(7 downto 0);
	signal displ: std_logic_vector(7 downto 0);


	begin
		va <= "11111111" when s1(3) = '1' else "00000000";
		displ <= s1 & s2;
		
		output <= va & displ;
end architecture arch;