library ieee;
library work;
use ieee.std_logic_1164.all;

entity opcode_dec is
port(
		op_code: in std_logic_vector(6 downto 0);
		
		-- intructions
		load_o, store_o, movr_o, add_o, sub_o, andi_o, ori_o, xori_o, noti_o: out std_logic;
		bgt_o, blo_o, beq_o, jsr_o, ret_o, push_o, pop_o, rts_o, str_o, hlt_o, loadn_o: out std_logic;
		
		-- control
		reg_s1_rd, reg_s2_rd, reg_ds_rd, reg_ds_wr: out std_logic
		
	);
end entity opcode_dec;

architecture arch of opcode_dec is
signal 	load, store, movr, add, sub, andi, ori, xori, noti, bgt, blo, beq: std_logic;
signal  jsr, ret, push, pop, rts, str, hlt, loadn, special: std_logic;
	
begin
		loadn <= '1' when op_code(6 downto 3) = B"0001" else '0';		
				
		movr <= '1' when op_code(6 downto 3) = B"0010" else '0';
			
		add <= '1' when op_code(6 downto 3) = B"0011" else '0';			
			
		sub <= '1' when op_code(6 downto 3) = B"0100" else '0';			
			
		andi <= '1' when op_code(6 downto 3) = B"0101" else '0';
			
		ori <= '1' when op_code(6 downto 3) = B"0110"  else '0';	
			
		xori <= '1' when op_code(6 downto 3) = B"0111" else '0';
				
		noti <= '1' when op_code(6 downto 3) = B"1000"  else '0';

		bgt <= '1' when op_code(6 downto 3) = B"1001" else '0';
			
		blo <= '1' when op_code(6 downto 3) = B"1010" else '0';
			
		beq <= '1' when op_code(6 downto 3) = B"1011" else '0';
		
---------------------------------------------------------------------------------------
------- last two bits used for opcode --------------------------------------------------

		special <= '1' when op_code(6 downto 3) = B"1111" else '0';
		
		jsr <= '1' when op_code(2 downto 0) = B"000" else '0';
		
		ret <= '1' when op_code(2 downto 0) = B"001" else '0';
			
		push <= '1' when op_code(2 downto 0) = B"010" else '0';

		pop <= '1' when op_code(2 downto 0) = B"011" else '0';
		
		hlt <= '1' when op_code(2 downto 0) = B"100" else '0';
		
		load <= '1' when op_code(2 downto 0) = B"101" else '0';
		
		store <= '1' when op_code(2 downto 0) = B"110" else '0';
		
----------------------------------------------------------------------------------------
				
		rts <= '1' when op_code(6 downto 3) = B"1100" else '0';
						
		str <= '1' when op_code(6 downto 3) = B"1101" else '0';
			
	loadn_o <= loadn;	
	movr_o <= movr;
	add_o <= add; 
	sub_o <= sub; 
	andi_o <= andi; 
	ori_o <= ori; 
	xori_o <= xori; 
	noti_o <= noti; 
	bgt_o <= bgt; 
	blo_o <= blo; 
	beq_o <= beq;
	
    jsr_o <= jsr and special; 
	ret_o <= ret and special; 
    push_o <= push and special;
    pop_o <= pop and special;
    hlt_o <= hlt and special;
    load_o <= load and special;
	store_o <= store and special; 
         
    rts_o <= rts;
    str_o <= str;

---- control ----------------------------
    reg_s1_rd <= movr or add or sub or andi or ori or xori or noti or bgt or blo or beq or (load and special) or (store and special);
    reg_s2_rd <= add or sub or andi or ori or xori or noti or bgt or blo or beq;
    reg_ds_rd <= bgt or blo or beq or rts or (jsr and special) or (push and special) or (store and special);
    reg_ds_wr <= loadn or movr or add or sub or andi or ori or xori or noti or str or (pop and special) or (load and special);   
      			
end architecture arch;