library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.all;

entity forward_logic is
port(
		s1_of: in std_logic_vector(3 downto 0);
		s2_of: in std_logic_vector(3 downto 0);
		ds_of: in std_logic_vector(3 downto 0);
		ds_wb: in std_logic_vector(3 downto 0);
		reg_wr_wb: in std_logic;
		sel_a, sel_b, sel_c: out std_logic
	);
end entity forward_logic;

architecture arch of forward_logic is

	signal v: std_logic_vector(15 downto 0);
	
begin 
	sel_a <= '1' when ((s1_of = ds_wb) and  (reg_wr_wb = '1')) else '0';
	sel_b <= '1' when ((s2_of = ds_wb) and  (reg_wr_wb = '1'))else '0';
	sel_c <= '1' when ((ds_of = ds_wb) and  (reg_wr_wb = '1'))else '0';
end architecture arch;