{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 17 17:28:31 2009 " "Info: Processing started: Thu Dec 17 17:28:31 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PipelineCPU -c PipelineCPU " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PipelineCPU -c PipelineCPU" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PipelineCPU.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PipelineCPU.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PipelineCPU-struct " "Info: Found design unit 1: PipelineCPU-struct" {  } { { "PipelineCPU.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 78 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PipelineCPU " "Info: Found entity 1: PipelineCPU" {  } { { "PipelineCPU.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "IFStage.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file IFStage.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 IFStage-struct " "Info: Found design unit 1: IFStage-struct" {  } { { "IFStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IFStage.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 IFStage " "Info: Found entity 1: IFStage" {  } { { "IFStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IFStage.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg-arch " "Info: Found design unit 1: reg-arch" {  } { { "reg.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg " "Info: Found entity 1: reg" {  } { { "reg.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "incrementer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file incrementer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 incrementer-arch " "Info: Found design unit 1: incrementer-arch" {  } { { "incrementer.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/incrementer.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 incrementer " "Info: Found entity 1: incrementer" {  } { { "incrementer.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/incrementer.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux_2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mux_2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_2-arch " "Info: Found design unit 1: mux_2-arch" {  } { { "mux_2.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/mux_2.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mux_2 " "Info: Found entity 1: mux_2" {  } { { "mux_2.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/mux_2.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "IDStage.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file IDStage.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 IDStage-struct " "Info: Found design unit 1: IDStage-struct" {  } { { "IDStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IDStage.vhd" 28 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 IDStage " "Info: Found entity 1: IDStage" {  } { { "IDStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IDStage.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "opcode_dec.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file opcode_dec.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 opcode_dec-arch " "Info: Found design unit 1: opcode_dec-arch" {  } { { "opcode_dec.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/opcode_dec.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 opcode_dec " "Info: Found entity 1: opcode_dec" {  } { { "opcode_dec.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/opcode_dec.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "OFStage.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file OFStage.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 OFStage-struct " "Info: Found design unit 1: OFStage-struct" {  } { { "OFStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/OFStage.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 OFStage " "Info: Found entity 1: OFStage" {  } { { "OFStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/OFStage.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg_file.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg_file.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg_file-arch " "Info: Found design unit 1: reg_file-arch" {  } { { "reg_file.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg_file.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg_file " "Info: Found entity 1: reg_file" {  } { { "reg_file.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg_file.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sign_ext.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sign_ext.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sign_ext-arch " "Info: Found design unit 1: sign_ext-arch" {  } { { "sign_ext.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/sign_ext.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sign_ext " "Info: Found entity 1: sign_ext" {  } { { "sign_ext.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/sign_ext.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_bench.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file test_bench.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 test_bench-tb " "Info: Found design unit 1: test_bench-tb" {  } { { "test_bench.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/test_bench.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 test_bench " "Info: Found entity 1: test_bench" {  } { { "test_bench.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/test_bench.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alu-arch " "Info: Found design unit 1: alu-arch" {  } { { "alu.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/alu.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 alu " "Info: Found entity 1: alu" {  } { { "alu.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/alu.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EXStage.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file EXStage.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 EXStage-struct " "Info: Found design unit 1: EXStage-struct" {  } { { "EXStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/EXStage.vhd" 40 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 EXStage " "Info: Found entity 1: EXStage" {  } { { "EXStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/EXStage.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sp.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sp.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sp-arch " "Info: Found design unit 1: sp-arch" {  } { { "sp.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/sp.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sp " "Info: Found entity 1: sp" {  } { { "sp.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/sp.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stack.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file stack.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 stack-arch " "Info: Found design unit 1: stack-arch" {  } { { "stack.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/stack.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 stack " "Info: Found entity 1: stack" {  } { { "stack.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/stack.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux_4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mux_4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux_4-arch " "Info: Found design unit 1: mux_4-arch" {  } { { "mux_4.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/mux_4.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mux_4 " "Info: Found entity 1: mux_4" {  } { { "mux_4.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/mux_4.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "WBStage.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file WBStage.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 WBStage-struct " "Info: Found design unit 1: WBStage-struct" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 WBStage " "Info: Found entity 1: WBStage" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "forward_logic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file forward_logic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 forward_logic-arch " "Info: Found design unit 1: forward_logic-arch" {  } { { "forward_logic.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/forward_logic.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 forward_logic " "Info: Found entity 1: forward_logic" {  } { { "forward_logic.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/forward_logic.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stall_unit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file stall_unit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 stall_unit-arch " "Info: Found design unit 1: stall_unit-arch" {  } { { "stall_unit.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/stall_unit.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 stall_unit " "Info: Found entity 1: stall_unit" {  } { { "stall_unit.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/stall_unit.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d_ff.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d_ff.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 d_ff-arch " "Info: Found design unit 1: d_ff-arch" {  } { { "d_ff.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/d_ff.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Info: Found entity 1: d_ff" {  } { { "d_ff.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/d_ff.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PipelineCPU " "Info: Elaborating entity \"PipelineCPU\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "IFStage IFStage:if_stage A:struct " "Info: Elaborating entity \"IFStage\" using architecture \"A:struct\" for hierarchy \"IFStage:if_stage\"" {  } { { "PipelineCPU.vhd" "if_stage" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 140 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "reg IFStage:if_stage\|reg:pc_reg A:arch " "Info: Elaborating entity \"reg\" using architecture \"A:arch\" for hierarchy \"IFStage:if_stage\|reg:pc_reg\"" {  } { { "IFStage.vhd" "pc_reg" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IFStage.vhd" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "zero reg.vhd(23) " "Warning (10540): VHDL Signal Declaration warning at reg.vhd(23): used explicit default value for signal \"zero\" because signal was never assigned a value" {  } { { "reg.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg.vhd" 23 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "incrementer IFStage:if_stage\|incrementer:if_incrementer A:arch " "Info: Elaborating entity \"incrementer\" using architecture \"A:arch\" for hierarchy \"IFStage:if_stage\|incrementer:if_incrementer\"" {  } { { "IFStage.vhd" "if_incrementer" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IFStage.vhd" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "mux_2 IFStage:if_stage\|mux_2:mux_new_pc A:arch " "Info: Elaborating entity \"mux_2\" using architecture \"A:arch\" for hierarchy \"IFStage:if_stage\|mux_2:mux_new_pc\"" {  } { { "IFStage.vhd" "mux_new_pc" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IFStage.vhd" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "IDStage IDStage:id_stage A:struct " "Info: Elaborating entity \"IDStage\" using architecture \"A:struct\" for hierarchy \"IDStage:id_stage\"" {  } { { "PipelineCPU.vhd" "id_stage" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 152 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "d_ff IDStage:id_stage\|d_ff:stall_reg A:arch " "Info: Elaborating entity \"d_ff\" using architecture \"A:arch\" for hierarchy \"IDStage:id_stage\|d_ff:stall_reg\"" {  } { { "IDStage.vhd" "stall_reg" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IDStage.vhd" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "mux_4 IDStage:id_stage\|mux_4:mux_instr A:arch " "Info: Elaborating entity \"mux_4\" using architecture \"A:arch\" for hierarchy \"IDStage:id_stage\|mux_4:mux_instr\"" {  } { { "IDStage.vhd" "mux_instr" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IDStage.vhd" 90 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "opcode_dec IDStage:id_stage\|opcode_dec:op_decoder A:arch " "Info: Elaborating entity \"opcode_dec\" using architecture \"A:arch\" for hierarchy \"IDStage:id_stage\|opcode_dec:op_decoder\"" {  } { { "IDStage.vhd" "op_decoder" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IDStage.vhd" 101 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "sign_ext IDStage:id_stage\|sign_ext:sign_extension A:arch " "Info: Elaborating entity \"sign_ext\" using architecture \"A:arch\" for hierarchy \"IDStage:id_stage\|sign_ext:sign_extension\"" {  } { { "IDStage.vhd" "sign_extension" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/IDStage.vhd" 112 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "OFStage OFStage:of_stage A:struct " "Info: Elaborating entity \"OFStage\" using architecture \"A:struct\" for hierarchy \"OFStage:of_stage\"" {  } { { "PipelineCPU.vhd" "of_stage" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 181 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "reg OFStage:of_stage\|reg:instruction_reg A:arch " "Info: Elaborating entity \"reg\" using architecture \"A:arch\" for hierarchy \"OFStage:of_stage\|reg:instruction_reg\"" {  } { { "OFStage.vhd" "instruction_reg" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/OFStage.vhd" 97 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "zero reg.vhd(23) " "Warning (10540): VHDL Signal Declaration warning at reg.vhd(23): used explicit default value for signal \"zero\" because signal was never assigned a value" {  } { { "reg.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg.vhd" 23 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "reg_file OFStage:of_stage\|reg_file:register_file A:arch " "Info: Elaborating entity \"reg_file\" using architecture \"A:arch\" for hierarchy \"OFStage:of_stage\|reg_file:register_file\"" {  } { { "OFStage.vhd" "register_file" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/OFStage.vhd" 102 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "reg OFStage:of_stage\|reg:forward_ds A:arch " "Info: Elaborating entity \"reg\" using architecture \"A:arch\" for hierarchy \"OFStage:of_stage\|reg:forward_ds\"" {  } { { "OFStage.vhd" "forward_ds" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/OFStage.vhd" 110 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "zero reg.vhd(23) " "Warning (10540): VHDL Signal Declaration warning at reg.vhd(23): used explicit default value for signal \"zero\" because signal was never assigned a value" {  } { { "reg.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg.vhd" 23 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "forward_logic OFStage:of_stage\|forward_logic:forward_control A:arch " "Info: Elaborating entity \"forward_logic\" using architecture \"A:arch\" for hierarchy \"OFStage:of_stage\|forward_logic:forward_control\"" {  } { { "OFStage.vhd" "forward_control" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/OFStage.vhd" 148 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "EXStage EXStage:ex_stage A:struct " "Info: Elaborating entity \"EXStage\" using architecture \"A:struct\" for hierarchy \"EXStage:ex_stage\"" {  } { { "PipelineCPU.vhd" "ex_stage" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 215 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "alu EXStage:ex_stage\|alu:alu_unit A:arch " "Info: Elaborating entity \"alu\" using architecture \"A:arch\" for hierarchy \"EXStage:ex_stage\|alu:alu_unit\"" {  } { { "EXStage.vhd" "alu_unit" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/EXStage.vhd" 161 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "WBStage WBStage:wb_stage A:struct " "Info: Elaborating entity \"WBStage\" using architecture \"A:struct\" for hierarchy \"WBStage:wb_stage\"" {  } { { "PipelineCPU.vhd" "wb_stage" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 259 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "reg WBStage:wb_stage\|reg:control_register A:arch " "Info: Elaborating entity \"reg\" using architecture \"A:arch\" for hierarchy \"WBStage:wb_stage\|reg:control_register\"" {  } { { "WBStage.vhd" "control_register" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 90 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "zero reg.vhd(23) " "Warning (10540): VHDL Signal Declaration warning at reg.vhd(23): used explicit default value for signal \"zero\" because signal was never assigned a value" {  } { { "reg.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/reg.vhd" 23 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "stack WBStage:wb_stage\|stack:stack A:arch " "Info: Elaborating entity \"stack\" using architecture \"A:arch\" for hierarchy \"WBStage:wb_stage\|stack:stack\"" {  } { { "WBStage.vhd" "stack" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 111 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "sp WBStage:wb_stage\|sp:SP_reg A:arch " "Info: Elaborating entity \"sp\" using architecture \"A:arch\" for hierarchy \"WBStage:wb_stage\|sp:SP_reg\"" {  } { { "WBStage.vhd" "SP_reg" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 146 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "stall_unit stall_unit:stall A:arch " "Info: Elaborating entity \"stall_unit\" using architecture \"A:arch\" for hierarchy \"stall_unit:stall\"" {  } { { "PipelineCPU.vhd" "stall" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/PipelineCPU.vhd" 288 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[0\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[0\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[1\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[1\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[2\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[2\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[3\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[3\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[4\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[4\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[5\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[5\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[6\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[6\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[7\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[7\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[8\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[8\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[9\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[9\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[10\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[10\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[11\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[11\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[12\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[12\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[13\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[13\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[14\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[14\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "WBStage:wb_stage\|RAM_data_WB\[15\] " "Warning: Converted tri-state buffer \"WBStage:wb_stage\|RAM_data_WB\[15\]\" feeding internal logic into a wire" {  } { { "WBStage.vhd" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/WBStage.vhd" 69 -1 0 } }  } 0 0 "Converted tri-state buffer \"%1!s!\" feeding internal logic into a wire" 0 0 "" 0 0}  } {  } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "WBStage:wb_stage\|stack:stack\|memory~25 " "Info: Inferred altsyncram megafunction from the following design logic: \"WBStage:wb_stage\|stack:stack\|memory~25\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Info: Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 16 " "Info: Parameter WIDTH_A set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 8 " "Info: Parameter WIDTHAD_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 256 " "Info: Parameter NUMWORDS_A set to 256" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 16 " "Info: Parameter WIDTH_B set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 8 " "Info: Parameter WIDTHAD_B set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 256 " "Info: Parameter NUMWORDS_B set to 256" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Info: Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Info: Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Info: Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/ram0_stack_775b040.hdl.mif " "Info: Parameter INIT_FILE set to db/ram0_stack_775b040.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0}  } { { "stack.vhd" "memory~25" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/stack.vhd" 18 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "WBStage:wb_stage\|stack:stack\|altsyncram:memory_rtl_0 " "Info: Elaborated megafunction instantiation \"WBStage:wb_stage\|stack:stack\|altsyncram:memory_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "WBStage:wb_stage\|stack:stack\|altsyncram:memory_rtl_0 " "Info: Instantiated megafunction \"WBStage:wb_stage\|stack:stack\|altsyncram:memory_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Info: Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 16 " "Info: Parameter \"WIDTH_A\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 8 " "Info: Parameter \"WIDTHAD_A\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 256 " "Info: Parameter \"NUMWORDS_A\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 16 " "Info: Parameter \"WIDTH_B\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 8 " "Info: Parameter \"WIDTHAD_B\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 256 " "Info: Parameter \"NUMWORDS_B\" = \"256\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Info: Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Info: Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Info: Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/ram0_stack_775b040.hdl.mif " "Info: Parameter \"INIT_FILE\" = \"db/ram0_stack_775b040.hdl.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hcm1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hcm1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hcm1 " "Info: Found entity 1: altsyncram_hcm1" {  } { { "db/altsyncram_hcm1.tdf" "" { Text "C:/Documents and Settings/Sladja/Desktop/racunarski VLSI sistemi/projekat VLSI/moj projekat/VLSI_CPU_project_2010/db/altsyncram_hcm1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1638 " "Info: Implemented 1638 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Info: Implemented 35 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "1553 " "Info: Implemented 1553 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Peak virtual memory: 187 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 17 17:29:05 2009 " "Info: Processing ended: Thu Dec 17 17:29:05 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Info: Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Info: Total CPU time (on all processors): 00:00:26" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
