library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg_file is
port(
		sel_s1: in std_logic_vector(3 downto 0);
		sel_s2: in std_logic_vector(3 downto 0);
		sel_s3: in std_logic_vector(3 downto 0);
		
		sel_dst: in std_logic_vector(3 downto 0);
		data_in: in std_logic_vector(15 downto 0);
		
		s1_out: out std_logic_vector(15 downto 0);
		s2_out: out std_logic_vector(15 downto 0);
		s3_out: out std_logic_vector(15 downto 0);
				
		clk, clr, wr: in std_logic
	);
end entity reg_file;
architecture arch of reg_file is
	
	type memory_element is array (0 to 15) of std_logic_vector(15 downto 0);
	
	signal memory: memory_element:= (others => (others => '0'));
	signal temp1: std_logic_vector(15 downto 0) := "0000000000000000" ;
	signal temp2: std_logic_vector(15 downto 0) := "0000000000000000" ;
	signal temp3: std_logic_vector(15 downto 0) := "0000000000000000" ;
	
	begin
	
	
	reg: process(clk, clr) is		
	begin
		if(clr = '1') then 
            memory(0) <= X"0000";
            memory(1) <= X"0000";
            memory(2) <= X"0000";
            memory(3) <= X"0000";
            memory(4) <= X"0000";
            memory(5) <= X"0000";
            memory(6) <= X"0000";
            memory(7) <= X"0000";
            memory(8) <= X"0000";
            memory(9) <= X"0000";
            memory(10) <= X"0000";
            memory(11) <= X"0000";
            memory(12) <= X"0000";
            memory(13) <= X"0000";
            memory(14) <= X"0000";
            memory(15) <= X"0000";
            
		elsif(rising_edge(clk)) then
			
			if(wr = '1') then 
				memory(to_integer(unsigned(sel_dst))) <= data_in;
			end if;
			temp1 <= memory(to_integer(unsigned(sel_s1)));
            temp2 <= memory(to_integer(unsigned(sel_s2)));
            temp3 <= memory(to_integer(unsigned(sel_s3)));
		end if;
			
	end process;
		
	s1_out <= temp1;
	s2_out <= temp2;
	s3_out <= temp3;
	
end architecture arch;