library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.all;
use ieee.std_logic_unsigned.all ;


entity incrementer is
port(
		input: in std_logic_vector(15 downto 0);
		output: out std_logic_vector(15 downto 0)
	);
end entity incrementer;

architecture arch of incrementer is
	signal va: std_logic_vector(15 downto 0);
	begin
		va <= input + 1;
		output <= va;
end architecture arch;
		 


