library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use work.all;


entity d_ff is
port(
		input: in std_logic;
		output: out std_logic;
		clk, clr: in std_logic
	);
end entity d_ff;

architecture arch of d_ff is

	signal v: std_logic;
	
begin
	r: process(clk, clr, v) is
	begin
        if(rising_edge(clk)) then 
            if(clr = '1') then v <= '0';
            else v <= input;
            end if;	
       end if;	
	output <= v;
	end process;
end architecture;