library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use work.all;


entity reg is
	generic (DATA_WIDTH : natural := 16);
	port(
		input: in std_logic_vector((DATA_WIDTH-1) downto 0);
		output: out std_logic_vector((DATA_WIDTH-1) downto 0):= (others => '0');
		clk, clr: in std_logic
		);
end entity reg;

architecture arch of reg is

	signal v: std_logic_vector((DATA_WIDTH-1) downto 0);
	signal zero: std_logic_vector((DATA_WIDTH-1) downto 0):= (others => '0');
begin
	r: process(clk, clr, v) is
	begin	
		if(rising_edge(clk)) then 
            if(clr = '1') then v <= zero;
		    else v <= input;
            end if;
		end if;		
		output <= v;
	end process;
end architecture;