library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.all;

entity mux_4 is
port(
		input1: in std_logic_vector(15 downto 0);
		input2: in std_logic_vector(15 downto 0);
		input3: in std_logic_vector(15 downto 0);
		input4: in std_logic_vector(15 downto 0);
		output: out std_logic_vector(15 downto 0);
		sel: in std_logic_vector(1 downto 0)
	);
end entity mux_4;

architecture arch of mux_4 is

	signal v: std_logic_vector(15 downto 0);
	
begin 

	v <= input4 when sel = "11" else 
         input3 when sel = "10" else
         input2 when sel = "01" else
         input1;
	output <= v;
end architecture arch;
