library ieee ;
library work;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity sp is
port(

		output: out std_logic_vector(7 downto 0);
		clk, clr, inc, dec: in std_logic

	);
end entity sp;

architecture arch of sp is
	
	signal sp_val: std_logic_vector(7 downto 0);
	
begin
	reg: process(clk, sp_val, clr) is
	begin
		if(rising_edge(clk)) then
            if(clr = '1') then sp_val <= B"00000000";
			elsif(inc = '1') then sp_val <= (UNSIGNED(sp_val) + 1);
			elsif(dec = '1') then sp_val <= (UNSIGNED(sp_val) - 1);		
            end if;
        end if;
		output <= sp_val;     
	end process;	
end architecture;